In general, a processor can access a memory through a memory interface to read out data to be processed or write processed data. This processor generates an internal address for the memory interface, and the memory interface generates appropriate control signals for accessing data corresponding to the internal address. These control signals activate a specific memory cell corresponding to the internal address.
Assume that the processor has a 23-bit internal address A[22:0]. The memory interface generates, for a DRAM type memory, a page number from A[22:12], a bank selection signal from A[11:10], a column number from A[9:2], and a word selection signal from A[1:0]. The memory interface generates, for an SRAM type memory, an SRAM address signal from A[22:2] and a word selection signal from lower 2-bit data A[1:0].
In contrast to the above memory interface, the processor always uses the same communication mode and internal address independently of the memory type to be used, e.g., a DRAM or SRAM. A data processing method executed in cooperation with a memory has been conventionally known (see, for example, European Patent Laid-Open No. 793390).
There is also disclosed a data processing apparatus (see, for example, Japanese Patent Laid-Open No. 2001-109656) which includes, in order to facilitate the design of a data processing apparatus which operates in cooperation with a memory, a plurality of processors for generating logical requests, a plurality of address processing circuits for generating macro commands as physical requests on the basis of the logical requests, an arbiter which receives a plurality of macro commands and selects one of the macro commands in accordance with an arbitration scheme, and an access interface for establishing access so as to specify part of the memory and its address by processing the plurality of macro commands in the order in which they are selected by the arbiter. According to this method, since access to the memory is made by converting a logical request from a processor into a physical request by using an address processing circuit, the processor is free from the influences of an access method and storage method for the memory. This improves the portability (versatility) of each processor.
According to the method disclosed in Japanese Patent Laid-Open No. 2001-109656, however, since data read/write addresses are generated by one functional block, the processor side must control to avoid read/write contention, resulting in complicated control. In addition, a plurality of data processing modules (processors) cannot be pipelined, and data must always be transferred through the memory interface. Furthermore, since a buffer memory is provided on the memory interface and shared among a plurality of processors, it is difficult to optimize the buffer memory.
If the number of data processing modules (processors) increases, not only the arbiter must be modified, but also a control circuit and buffer memory must be added, resulting in difficulty in making a modification. When a module that needs to simultaneously acquire a plurality of (discontinuous) data, e.g., a resizing or filter module, is to be added, the above address generating circuit as well as the buffer memory becomes complicated.
In order to obtain a good image output when image data taken by a digital camera or the like is output by a printer, various types of image processing are generally required. FIG. 22 is a block diagram showing the arrangement of a conventional image processor which performs image processing when image data taken by a digital camera is to be output by a printer.
First of all, a JPEG decoder 201 decodes JPEG image data (data taken by the digital camera) input from an input unit 200. The decoded data are output in the order of Y, Cr, and Cb blocks and hence temporarily stored in an MCU buffer 203. A pixel sequential unit 202 then reads out these data as pixel sequential YCrCb data. If Cr and Cb color difference data are sub-sampled, they are output after being interpolated at the read time. The pixel sequential image data are output in MCU order and hence temporarily stored in an MCU line buffer 205. A rasterizing unit 204 then reads them out as rasterized YCrCb data. The rasterized image data are subjected to color adjustment such as white balance adjustment in a color adjustment unit 206 and contrast adjustment in a contrast adjustment unit 207. The resultant data are converted into RGB data by an RGB converter 208.
If the orientation of printing differs from that of an image, orientation matching is made by a rotating unit 209 using a frame buffer 210. For an image with noticeable noise, noise reduction processing is performed by a noise reducer 211. At this time, a line interface unit 233 is used to refer to neighboring pixel data.
A resizing unit 212 then resizes the image into an image having a size matched with a printing resolution. At this time, a line buffer 213 is used to refer to neighboring pixel data. A clipping unit 214 removes (trims) a portion that is unnecessary to be output from the resized image data. In addition, in order to save the capacity of a page memory, data in an effective band area is extracted in band processing in which part of a page is sequentially cut out on a band and processed.
A background compositing unit 215 composites background data with the clipped image data. A frame compositing unit 217 composites frame data with the image data. The resultant data is stored in a band buffer 219. When an image having small images tiled is to be used as background data, a tiling unit 216 is used to repeatedly reading out the background data in the horizontal and vertical directions. The resultant data is used. When the frame data needs to be resized in accordance with various paper sizes and layouts, the frame data is resized by a resizing unit 218 before composited with image data. At this time, a line buffer 220 is used to refer to neighboring pixel data.
The print image data stored in the band buffer 219 is converted into a density linear signal by an input γ converter 221. This signal is converted into color material data (output device color) of the printer by a color converter 222. This data is subjected to output γ correction in an output γ converter 223. The resultant data is converted into bitmap data (dot pattern) by a halftone processor 224. In this case, if an error diffusion method is used for halftone processing of the image data, a line buffer 225 is used to diffuse a quantization error into neighboring pixels. The bitmap data is temporarily stored in a band buffer 226.
When a print engine (not shown) is started, an H-V converter 228 reads out the bitmap data from the band buffer 226 in accordance with the arrangement of the dot constituent elements (e.g., nozzles in an ink-jet scheme) of the head in synchronism with a sync signal from the print engine, and stores the data in a block buffer 230. In general, since bitmap data is stored in the band buffer 226 with a plurality of dots in the scan direction of the head being one word, data in the dot constituent element array (nozzle array) direction of the head is extracted. In addition, a registration unit 229 shifts the positions of bits simultaneously read out for each dot constituent element array (nozzle array) of the head, thereby performing registration.
When a print image is to be formed in a plurality of passes (scans of the head) to reduce streaks and unevenness at the time of printout, a pass divider 231 distributes the output dots of the bitmap data to a plurality of passes in accordance with the mask signal generated by a mask generator 232. The divided dot data are converted into a transmission format for the head by a line interface unit 233, and output to the head by an output unit 234.
When complicated processing like that described above is to be performed, the respective types of processing are implemented into modules to facilitate development and maintenance. For example, an image processing method is disclosed (see, for example, Japanese Patent Laid-Open No. 9-116660), in which each type of image processing is implemented into a module, and the respective modules are connected to each other through buffer memories, thereby facilitating updating.
The method disclosed in Japanese Patent Laid-Open No. 9-116660 has a drawback that many buffer memories are required in proportion to the number of image processing modules. In addition, an enormous local memory is required to cope with an arbitrary image size. For example, the line buffers 205 and 213 and frame buffer 210 in FIG. 22 depend on the input image size, and the band buffers 219 and 226 and line buffer 225 depend on the output size (e.g., the paper size, output resolution, and band height). In order to match these buffers with image data having various sizes, a buffer memory capacity corresponding to the maximum size must be estimated.
The necessary image processing contents differ depending on each output image. If, for example, the orientation of printing coincides with the orientation of an input image, no rotation processing is required. In addition, if there are no background, frame, and the like, no compositing processing is required. In such a case, in the prior art, unnecessary processing is performed by making parameter setting for nothing in effect, e.g., performing 0° rotation and setting an α value for opaque.
According to the method disclosed in Japanese Patent Laid-Open No. 9-116660, it is impossible to replace some function after the completion of hardware. Assume that a specification change has occurred in an RGB conversion module. In this case, if the above series of processing modules is implemented by hardware, it is impossible to replace only the RGB conversion module with another processing (software processing). As a consequence, the series of processing modules including the RGB conversion module is wasted. If a critical defect is caused in some module, all the associated processing modules become unusable.
In a conventional image processing apparatus designed to generate desired data by performing image processing such as clipping processing, resizing processing, and rotation processing with respect to blocked image data, each image processing operation is performed after the input blocked image data is rasterized.
According to the conventional image processing method, however, since image processing is performed after rasterization, it takes much time to perform overall image processing, and many memories for processing which are required for image processing must be mounted in the image processing apparatus. In addition, when permutation processing such as rotation is to be performed, the conventional method requires a buffer for permutation processing. If permutation is executed by using write addresses in order to omit the buffer for permutation processing, since the addresses do not become continuous, a burst mode cannot be used. This increases the access time.